1. Field of the Invention
The present invention relates to a failure diagnosing system for logic circuits. Japanese Patent Application Nos. JP2006-300044 and JP2006-300094 are related to this application. The disclosures of these applications are incorporated herein by reference.
2. Description of the Art
In failure diagnosis of logic circuits, a computer is used in which a logic circuit failure diagnosis program is installed. Necessary commands for desired failure diagnosis are inputted from an input unit to the computer to perform the failure diagnosis.
FIG. 1 is a flowchart of a failure portion estimating method for logic circuits in a related art. A failure simulator is used for failure diagnosis to logic circuits. First, at a step S101, an assumption is made on occurrence of a failure in the logic circuits and a functional simulation or logic simulation of the logic circuits is performed. Then, the simulation results are compared with expected results prepared in advance. An assumed position of the failure is related to input and output test vectors, and a combination of them is stored in a failure dictionary. Next, at a step S102, failure data is obtained from actual test results of the logic circuits. At a step S103, the failure dictionary is searched based on input and output vectors for a failure and an estimated failure is determined. Then, at a step S104, candidates of the estimated failure are ordered to estimate a failure portion.
In addition, as another method to specify a failure portion in logic circuits, a method is known which uses an electron beam tester to estimate a failure portion from the uppermost layer of the logic circuits while observing an internal signal in the interface between wiring layers, so that the failure portion is sequentially narrowed into a lower wiring layer of the logic circuits.
In conjunction with the above description, the following proposals have been made.
A Japanese Laid Open Patent Application (JP-A-Heisei B-146093) discloses a failure estimating method of a sequential circuit. In this technique in this related art, a semiconductor integrated circuit is divided into a group of latches and combination circuits to estimate a failure by using all expected values of all latches to all vectors, tester pass/failure data, and connection data of all circuits. The failure estimating method includes first to sixth procedures for every failure vector as processing procedures to determine failure propagation estimated values in the interface of the combination circuit, and finally, a failure estimation list is generated. Here, in the first procedure, combination circuits are extracted from an actual failure output pin or a latch input line estimated to be a failure to input pins of the semiconductor integrated circuit or a latch output in an input direction, and the combination circuits are further extracted from the input of the extracted combination circuits to output pins of the semiconductor integrated circuit or a latch input in an output direction. In the second procedure, a data flow is generated by checking whether or not the outputs of the latches connected to outputs of the combination circuits have affects to any other latches. In the third procedure, failure propagation values in an interface of the combination circuit are estimated and confirmed through a simulation to select a combination of simultaneous failure propagation possible signal lines, based on confirmation of single failure propagation, confirmation of branching in the same signal line and confirmation of branched signal activation in the combination circuit, and clock enable confirmation of latches in the interface. In the fourth procedure, the combination circuit is extracted in a rear direction if extraction of the circuit in the rear direction to the output of the actual semiconductor integrated circuit is not confirmed. In the fifth procedure, it is determined whether or not a result of the failure propagation simulation using the failure estimation results in the input interface of the combination circuit is consistent with an actual failure output. In the sixth procedure, a latch state estimation value table is generated if consistency is determined in the fifth procedure, and the presence or absence of degeneration failure is determined through the simulation result of the respective signal lines in the combination circuit using the latch state estimation value table in order to estimate failure portions in the combination circuits.
In a logic circuit manufacturing process, logic circuits are subjected to physical tests such as a visual test and electric tests by LSI testers for the purpose of improvement the yield of logic circuits. Although a physical failure of the logic circuit can be detected through the physical tests, the physical failure does not necessarily indicate abnormality of a logical operation. Moreover, it is impossible to determine where a failure portion exists in the logic circuit by simply applying electric test to the logic circuit.
Therefore, a technique to associate the physical failure with a logical failure is proposed in Japanese Laid Open Patent Applications (JP-A-Heisei 11-214465 and JP-P2002-530659A).
In the Japanese Laid Open Patent Application (JP-A-Heisei 11-214465), a diagnosis program is proposed to determine a failure portion by using a logic LSI as a monitor in a logic LSI manufacturing process. Electric characteristics of the logic circuit are measured, and if a concentric or rectangular region from the central coordinate of the visual failure obtained from a visual test of the logic circuit is consistent with the failure portion obtained from an electric test result, the failure results from the visual failure.
In Japanese Laid Open Patent Application (JP-P2002-530659A), a method is proposed to extract failure candidates of a logic circuit by using a diagnosis function of an ATPG (automatic test pattern generation) tool in order to compare the failure candidates with a physically abnormal portion obtained from an in-line test. A distance from the failure portion is specified by a user, and if the failure candidates are present within the specified radius, it is determined that the failure results from the visual abnormality.
The present inventors have recognized as follows. In order to improve a manufacture yield of a logic circuit, it is necessary to detect a failure observed in designing and manufacturing processes of the logic circuit. The conventional logic circuit failure diagnosing system allows a highly possible portion causing a logical abnormality to be narrowed in the level of circuit block or networks with respect to the logic circuit. It is further possible to obtain logic values of failure candidates and a failure pattern at the time of occurrence of the failure as auxiliary data. However, it is not necessarily possible to specify one failure candidate to a single network or instance by simply applying a simulation using logics and layouts, and a plurality of failure candidates are obtained in many cases. It is also difficult to systematically analyze defects, i.e. failures, observed in the designing and manufacturing processes only from diagnosis results of individual LSI.
Moreover, process abnormality is estimated by an engineer from a failure distribution within a wafer obtained from the visual test in a test process, and chips which are subjected to a failure diagnosis are selected by an engineer. However, even if the selected chips are analyzed, it is not necessarily possible to specify a failure cause which affects manufacturing quality, and a failure diagnosis needs to be carried out for multiple chips.